Cell Circuit and Layout with Linear Finfet Structures

ABSTRACT

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

CLAIM OF PRIORITY

This application is a continuation application under 35 U.S.C. 120 ofprior U.S. application Ser. No. 15/426,674, filed on Feb. 7, 2017, whichis a continuation application under 35 U.S.C. 120 of prior U.S.application Ser. No. 12/775,429, filed on May 6, 2010, issued as U.S.Pat. No. 9,563,733, on Feb. 7, 2017, which claims priority under 35U.S.C. 119(e) to U.S. Provisional Patent Application No. 61/176,058,filed May 6, 2009. The disclosure of each above-identified patentapplication is incorporated herein by reference in its entirety for allpurposes.

BACKGROUND

It is known that optical lithography has reached the end of itscapability at the 193 nm light wavelength and 1.35 numerical aperture(NA) immersion system. The minimum straight line resolution capabilityof this equipment is approximately 40 nm with an approximate 80 nmfeature-to-feature pitch. A feature-to-feature pitch requirement lowerthan about 80 nm would require multiple patterning steps for a givenstructure type within a given chip level. Also, line end resolutionbecomes more challenging as lithography is pushed toward its resolutionlimits. One solution to line end shortening is to add a subsequentpatterning step to cut features so as to form the line ends. Such lineend cutting allows two line ends to be placed in closer proximity, andtherefore may improve overall feature placement density, but at the costof an additional patterning step. It should be understood that the addedlithography steps for multiple patterning and/or line end cuttingincreases manufacturing cost, possibly to the point where anyimprovement in feature placement density is financially negated.

In semiconductor device layout, a typical metal line pitch at the 32 nmcritical dimension is approximately 100 nm. In order to achieve the costbenefit of feature scaling, a scaling factor of 0.7 to 0.75 isdesirable. The scaling factor of about 0.75 to reach the 22 nm criticaldimension would require a metal line pitch of about 75 nm, which isbelow the capability of current single exposure lithography systems andtechnology.

SUMMARY

In one embodiment, a cell circuit of a semiconductor device isdisclosed. The cell circuit includes a substrate, and a number oflinear-shaped diffusion fins defined to extend over the substrate in afirst direction so as to extend parallel to each other. Each of thenumber of linear-shaped diffusion fins is defined to project upward fromthe substrate along their extent in the first direction. The cellcircuit also includes a number of gate level structures defined toextend in a conformal manner over some of the number of linear-shapeddiffusion fins. Portions of each gate level structure that extend overany of the number of linear-shaped diffusion fins extend in a seconddirection that is substantially perpendicular to the first direction.Portions of each gate level structure that extend over any of the numberof linear-shaped diffusion fins form gate electrodes of a correspondingtransistor.

In one embodiment, a semiconductor device cell layout is disclosed. Thecell layout includes a diffusion level layout and a gate level layout.The diffusion level layout includes a number of diffusion fin layoutshapes defined to extend in only a first direction across the celllayout so as to extend parallel to each other. Each of the number ofdiffusion fin layout shapes corresponds to diffusion fin structuresdefined to project upward from a substrate along their extent in thefirst direction. The gate level layout includes a number of gate levellayout shapes defined to extend in a second direction across the celllayout that is substantially perpendicular to the first direction. Eachof the gate level layout shapes corresponds to gate level structuresdefined to extend in a conformal manner over some of the diffusion finstructures that correspond to the diffusion fin layout shapes. Portionsof each gate level structure that extend over any of the diffusion finstructures form gate electrodes of a corresponding transistor.

Other aspects and advantages of the invention will become more apparentfrom the following detailed description, taken in conjunction with theaccompanying drawings, illustrating by way of example the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B show a layout view of a finfet transistor, in accordancewith one embodiment of the present invention;

FIG. 2A shows an exemplary cell layout incorporating finfet transistors,in accordance with one embodiment of the present invention;

FIG. 2B shows a vertical cross-section view B-B as called out in FIG.2A, in accordance with one embodiment of the present invention;

FIG. 2C shows a vertical cross-section view C-C as called out in FIG.2A, in accordance with one embodiment of the present invention;

FIG. 3A shows an example of gate electrode tracks defined within therestricted gate level layout architecture, in accordance with oneembodiment of the present invention; and

FIG. 3B shows the exemplary restricted gate level layout architecture ofFIG. 3A with a number of exemplary gate level features defined therein,in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the present invention. Itwill be apparent, however, to one skilled in the art that the presentinvention may be practiced without some or all of these specificdetails. In other instances, well known process operations have not beendescribed in detail in order not to unnecessarily obscure the presentinvention.

A “finfet” is a transistor constructed from a vertical silicon island.The finfet transistor can also be referred to as a tri-gate transistor.FIGS. 1A and 1B show a layout view of a finfet transistor 100, inaccordance with one embodiment of the present invention. The finfettransistor 100 is constructed from a diffusion island 102 and a gateelectrode layer 104. The diffusion island 102 projects vertically upwardfrom a substrate 105, as shown in FIG. 1B. A gate oxide layer 106 isdisposed between the diffusion island 102 and the gate electrode layer104. The diffusion island 102 can be doped to form either a p-typetransistor or an n-type transistor. The portion of the gate electrodelayer 104 that covers the diffusion island 102 forms the gate electrodeof the finfet transistor 100. Therefore, the gate electrode of thefinfet transistor 100 exists on three sides of the diffusion island 102,thereby providing for control of the finfet transistor channel fromthree sides, as opposed to from one side as in a non-finfet transistor.

Transistor scaling has slowed below the 45 nanometers (nm) criticaldimension due to gate oxide limitations and/or source/drain leakagescaling issues. The finfet transistor mitigates these issues bycontrolling the channel of the finfet transistor from three sides. Theincreased electrical fields in the channel of the finfet transistorimprove the relationship between I-on (on drive current) and I-off(sub-threshold leakage current). Finfet transistors can be employed atthe 22 nm critical dimension and below. However, due to their verticalprojection, finfet transistors can have restricted placement in variouscircuit layouts. For instance, there can be a required finfet-to-finfetminimum spacing and/or a required finfet-to-finfet minimum pitch, amongother restrictions. Embodiments are disclosed herein for cell layoutsthat utilize finfet transistors in a manner which complements layoutscaling.

FIG. 2A shows an exemplary cell layout incorporating finfet transistors,in accordance with one embodiment of the present invention. The celllayout is defined by a cell width W and a cell height H. The cell layoutincludes a diffusion level within which a number of diffusion islands102 are defined for subsequent formation of finfet transistors andassociated connections. The diffusion islands 102 are also referred toas diffusion fins 102. In an as-drawn layout state, the diffusion fins102 are linear-shaped. The diffusion fins 102 are oriented to beparallel to each other such that their lengths extend in the directionof the cell width W.

In one embodiment, the diffusion fins 102 are placed along a number ofdiffusion tracks 201A-201H. The diffusion tracks 201A-201H representvirtual lines that extend in the direction of the cell width W and areequally spaced at a fixed pitch. The pitch of the diffusion tracks201A-201H is related to the cell height H, such that the diffusion trackpitch can be continued across cell boundaries. Therefore, the diffusionfins 102 for multiple neighboring cells will be placed in accordancewith a common global set of equally spaced diffusion tracks, therebyfacilitating chip level manufacturing of the diffusion fins 102 inmultiple cells.

It should be understood that the diffusion fins 102 can be placed asneeded, so long as they are placed in accordance with the diffusiontracks 201A-201H which have the controlled spatial relationship with thecell height H. Therefore, some diffusion tracks 201A-201H may not have adiffusion fin 102 placed thereon. Also, portions of some diffusiontracks 201A-201H may be vacant with regard to diffusion fin 102placement. In other words, some diffusion tracks 201A-201H will have oneor more portions occupied by diffusion fins 102 and one or more portionsnot occupied by diffusion fins 102.

The cell layout also includes a number of linear-shaped gate electrodestructures 104. The linear-shaped gate electrode structures 104 extendin a substantially perpendicular direction to the diffusion fins 102,i.e., in the direction of the cell height H. The linear-shaped gateelectrode structures 104 wrap over the diffusion fins 102 to form gateelectrodes of finfet transistors. It should be understood that anappropriate gate oxide material is disposed between the diffusion fins102 and the gate electrode structures 104 formed thereover.

In one embodiment, the linear-shaped gate electrode structures 104 areplaced in accordance with a gate level virtual grate defined by a set ofparallel equally spaced virtual lines 202A-202T that extend in thedirection of the cell height H. The set of virtual lines 202A-202T ofthe gate level virtual grate are spaced at a fixed gate pitch. In oneembodiment, the gate pitch is related to the cell width W, such that thegate pitch can be continued across cell boundaries. Therefore, the gateelectrode structures 104 for multiple neighboring cells will be placedin accordance with a common global set of equally spaced gate levelvirtual grate lines, thereby facilitating chip level manufacturing ofthe linear-shaped gate electrode structures 104 in multiple cells.

It should be understood that some of the gate level virtual grate lines202A-202T may be occupied by gate electrode structures 104, while othersof the gate level virtual grate lines 202A-202T are left vacant. Also,along a given gate level virtual grate line 202A-202T, one or morelinear-shaped gate electrode structures 104 can be placed as needed andspaced apart as needed.

The cell layout also includes a number of linear-shaped localinterconnect structures 203. The local interconnect structures 203 areoriented parallel to the gate electrode structures 104. In oneembodiment, placement of the local interconnect structures 203 isdefined to be out of phase from placement of the gate electrodestructures 104 by one-half of the gate pitch. Thus, in this embodiment,each local interconnect structure 203 is centered between itsneighboring gate level virtual grate lines 202A-202T. And, if itsneighboring gate level virtual grate lines 202A-202T are occupied bygate electrode structures 104, the local interconnect structure 203 willbe correspondingly centered between the neighboring gate electrodestructures 104. Therefore, in this embodiment, adjacently placed localinterconnect structures 203 will have a center-to-center spacing equalto the gate pitch.

In one embodiment, the cell layout also includes a number oflinear-shaped metal 1 (M1) interconnect structures 205. The M1interconnect structures 205 are oriented parallel to the diffusion fins102 and perpendicular to the gate electrode structures 104. In oneembodiment, placement of the M1 interconnect structures 205 is definedto be out of phase from placement of the diffusion fins 102 by one-halfof the diffusion track 201A-201H pitch. Thus, in this embodiment, eachM1 interconnect structure 205 is centered between its neighboringdiffusion tracks 201A-201H. And, if its neighboring diffusion tracks201A-201H are occupied by diffusion fins 102, the M1 interconnectstructure 205 will be correspondingly centered between its neighboringdiffusion fins 102, albeit within a higher chip level. Therefore, inthis embodiment, adjacently placed M1 interconnect structures 205 willhave a center-to-center spacing equal to the diffusion track pitch. Inone embodiment, the M1 interconnect structure 205 pitch, and hence thediffusion track pitch, is set at the single exposure lithographic limit,e.g., 80 nm for 193 nm wavelength light and 1.35 NA. In this embodiment,no double exposure lithography, i.e., multiple patterning, is requiredto manufacture the M1 interconnect structures 205.

The cell layout also includes a number of contacts 207 defined toconnect various M1 interconnect structures 205 to various localinterconnect structures 203 and gate electrode structures 104, therebyproviding electrical connectivity between the various finfet transistorsas necessary to implement the logic function of the cell. In oneembodiment, the contacts 205 are defined to satisfy single exposurelithographic limits. For example, in one embodiment, layout features towhich the contacts 207 are to connect are sufficiently separated toenable single exposure manufacture of the contacts 207. For instance,the M1 interconnect structures 205 are defined such that their line endswhich are to receive contacts 207 are sufficiently separated fromneighboring M1 interconnect structure 205 line ends which are also toreceive contacts 207, such that a spatial proximity between the contacts207 is sufficiently large to enable single exposure lithography of thecontacts 207. In one embodiment, neighboring contacts 207 are separatedfrom each other by at least 1.5 times the gate pitch. It should beappreciated that line end cutting and the associated increased expenseof double exposure lithography can be eliminated by sufficientlyseparating opposing line ends of the M1 interconnect structures 205.

As previously mentioned, the cell height H and diffusion track pitch,i.e., diffusion fin pitch, are related. In one embodiment, the cellheight H is an integer multiple of the diffusion track pitch. The celllayout techniques described herein can be used to reduce the cell heightH by the approximate difference between the single exposure lithographiccapability and an applicable scaling requirement. For example, considerthat the cell height H is based on the single exposure straight linelithographic limit, e.g., 80 nm diffusion fin pitch. Therefore, thediffusion track pitch of the cell cannot be scaled down further withoutincurring the cost of multiple patterning. However, the cell layouttechniques described herein can be utilized to scale down the overallsize of the cell layout while maintaining the single exposure straightline lithographic limit with regard to the diffusion track pitch.

For example, if a 9 diffusion track cell was used at 32 nm, then ascaled down version of the cell having 8 tracks at 22 nm is created toprovide the overall cell layout scaling requirements. Specifically, theM1 interconnect structure 205 layout of the cell is drawn in fewertracks, e.g., 8 tracks rather than 9 tracks, and the opposing line endsof the M1 interconnect structures 205 are arranged so that the singleexposure lithography design rules can be satisfied. Reduction of thecell height H by one diffusion track can add up to significant layoutarea savings across the chip.

FIG. 2B shows a vertical cross-section view B-B as called out in FIG.2A, in accordance with one embodiment of the present invention. Thediffusion fins 102 are shown to project upward from the substrate 105.An insulating material 211, such as an oxide, is disposed between andaround the diffusion fins 102 to provide structural support andelectrical insulation. The local interconnect feature 203 is shown toextend perpendicular to the diffusion fins 102 and across the tops ofthe diffusion fins 102 so as to establish electrical connections betweenthe local interconnect feature 203 and each of the diffusion fins 102.The contact 207 is shown to extend vertically through the layout toelectrically connect the M1 interconnect structure 205 to the localinterconnect structure 203. The contact 207 and M1 interconnectstructure 205 are also surrounded by the insulating material 211, whichagain provides structural support and electrical insulation. It shouldbe appreciated that the M1 interconnect structure 205 is positioned in acentered manner with respect to its neighboring underlying diffusionfins 102, as discussed above.

FIG. 2C shows a vertical cross-section view C-C as called out in FIG.2A, in accordance with one embodiment of the present invention. Thediffusion fin 102 is shown to project upward from the substrate 105. Thegate oxide material 106 is disposed conformally over the diffusion fin102. The gate electrode structure 104 is shown to extend perpendicularto the diffusion fin 102 and conformally over the diffusion fin 102. Thecontact 207 is shown to extend vertically to electrically connect the M1interconnect structure 205 to the gate electrode structure 104. Theinsulating material 211, such as an oxide, is disposed over and aroundthe gate electrode structure 104, the contact 207, and the M1interconnect structure 205 to provide structural support and electricalinsulation.

It should be understood that the relative sizes of the different layoutfeatures as shown in FIGS. 2A-2C are exemplary, and in no way limit theprinciples of the present invention as disclosed herein. For example, inother embodiments, the M1 power lines shown at the top and bottom of thecell layout in FIG. 2A can be of different width, e.g., larger width,than the M1 lines within an interior of the cell. Additionally, therelative vertical heights of the layout features as shown in thecross-sections of FIGS. 2B and 2C can vary from what is depictedtherein. For example, in FIG. 2C, the gate electrode 104 may extendfurther vertically than what is shown.

Restricted Gate Level Layout Architecture

The cell layout incorporating finfet transistors, as discussed above,can implemented a restricted gate level layout architecture. For thegate level, a number of parallel virtual lines are defined to extendacross the layout. These parallel virtual lines are referred to as gateelectrode tracks, as they are used to index placement of gate electrodesof various transistors within the layout. In one embodiment, such as thecell layout discussed above with regard to FIG. 2A, the parallel virtuallines which form the gate electrode tracks are defined by aperpendicular spacing therebetween equal to a specified gate electrodepitch. Therefore, placement of gate electrode segments on the gateelectrode tracks corresponds to the specified gate electrode pitch. Inanother embodiment the gate electrode tracks can be spaced at variablepitches greater than or equal to a specified gate electrode pitch.

FIG. 3A shows an example of gate electrode tracks 301A-301E definedwithin the restricted gate level layout architecture, in accordance withone embodiment of the present invention. Gate electrode tracks 301A-301Eare formed by parallel virtual lines that extend across the gate levellayout of the chip, with a perpendicular spacing therebetween equal to aspecified gate electrode pitch 307.

Within the restricted gate level layout architecture, a gate levelfeature layout channel is defined about a given gate electrode track soas to extend between gate electrode tracks adjacent to the given gateelectrode track. For example, gate level feature layout channels 301A-1through 301E-1 are defined about gate electrode tracks 301A through301E, respectively. It should be understood that each gate electrodetrack has a corresponding gate level feature layout channel. Also, forgate electrode tracks positioned adjacent to an edge of a prescribedlayout space, e.g., adjacent to a cell boundary, the corresponding gatelevel feature layout channel extends as if there were a virtual gateelectrode track outside the prescribed layout space, as illustrated bygate level feature layout channels 301A-1 and 301E-1. It should befurther understood that each gate level feature layout channel isdefined to extend along an entire length of its corresponding gateelectrode track. Thus, each gate level feature layout channel is definedto extend across the gate level layout within the portion of the chip towhich the gate level layout is associated.

Within the restricted gate level layout architecture, gate levelfeatures associated with a given gate electrode track are defined withinthe gate level feature layout channel associated with the given gateelectrode track. A contiguous gate level feature can include both aportion which defines a gate electrode of a transistor, i.e., of afinfet transistor as disclosed herein, and a portion that does notdefine a gate electrode of a transistor. Thus, a contiguous gate levelfeature can extend over both a diffusion region, i.e., diffusion fin,and a dielectric region of an underlying chip level.

In one embodiment, each portion of a gate level feature that forms agate electrode of a transistor is positioned to be substantiallycentered upon a given gate electrode track. Furthermore, in thisembodiment, portions of the gate level feature that do not form a gateelectrode of a transistor can be positioned within the gate levelfeature layout channel associated with the given gate electrode track.Therefore, a given gate level feature can be defined essentiallyanywhere within a given gate level feature layout channel, so long asgate electrode portions of the given gate level feature are centeredupon the gate electrode track corresponding to the given gate levelfeature layout channel, and so long as the given gate level featurecomplies with design rule spacing requirements relative to other gatelevel features in adjacent gate level layout channels. Additionally,physical contact is prohibited between gate level features defined ingate level feature layout channels that are associated with adjacentgate electrode tracks.

FIG. 3B shows the exemplary restricted gate level layout architecture ofFIG. 3A with a number of exemplary gate level features 309-323 definedtherein, in accordance with one embodiment of the present invention. Thegate level feature 309 is defined within the gate level feature layoutchannel 301A-1 associated with gate electrode track 301A. The gateelectrode portions of gate level feature 309 are substantially centeredupon the gate electrode track 301A. Also, the non-gate electrodeportions of gate level feature 309 maintain design rule spacingrequirements with gate level features 311 and 313 defined withinadjacent gate level feature layout channel 301B-1. Similarly, gate levelfeatures 311-323 are defined within their respective gate level featurelayout channel, and have their gate electrode portions substantiallycentered upon the gate electrode track corresponding to their respectivegate level feature layout channel. Also, it should be appreciated thateach of gate level features 311-323 maintains design rule spacingrequirements with gate level features defined within adjacent gate levelfeature layout channels, and avoids physical contact with any anothergate level feature defined within adjacent gate level feature layoutchannels.

A gate electrode corresponds to a portion of a respective gate levelfeature that extends over a diffusion structure, i.e., over a diffusionfin, wherein the respective gate level feature is defined in itsentirety within a gate level feature layout channel. Each gate levelfeature is defined within its gate level feature layout channel withoutphysically contacting another gate level feature defined within anadjoining gate level feature layout channel. As illustrated by theexample gate level feature layout channels 301A-1 through 301E-1 of FIG.3B, each gate level feature layout channel is associated with a givengate electrode track and corresponds to a layout region that extendsalong the given gate electrode track and perpendicularly outward in eachopposing direction from the given gate electrode track to a closest ofeither an adjacent gate electrode track or a virtual gate electrodetrack outside a layout boundary.

Some gate level features may have one or more contact head portionsdefined at any number of locations along their length. A contact headportion of a given gate level feature is defined as a segment of thegate level feature having a height and a width of sufficient size toreceive a gate contact structure. In this instance, “width” is definedacross the substrate in a direction perpendicular to the gate electrodetrack of the given gate level feature, and “height” is defined acrossthe substrate in a direction parallel to the gate electrode track of thegiven gate level feature. The gate level feature width and height may ormay not correspond to the cell width W and cell height H, depending onthe orientation of the gate level features within the cell. It should beappreciated that a contact head of a gate level feature, when viewedfrom above, can be defined by essentially any layout shape, including asquare or a rectangle. Also, depending on layout requirements andcircuit design, a given contact head portion of a gate level feature mayor may not have a gate contact defined thereabove.

A gate level of the various embodiments disclosed herein is defined as arestricted gate level, as discussed above. Some of the gate levelfeatures form gate electrodes of transistor devices. Others of the gatelevel features can form conductive segments extending between two pointswithin the gate level. Also, others of the gate level features may benon-functional with respect to integrated circuit operation. It shouldbe understood that the each of the gate level features, regardless offunction, is defined to extend across the gate level within theirrespective gate level feature layout channels without physicallycontacting other gate level features defined with adjacent gate levelfeature layout channels.

In one embodiment, the gate level features are defined to provide afinite number of controlled layout shape-to-shape lithographicinteractions which can be accurately predicted and optimized for inmanufacturing and design processes. In this embodiment, the gate levelfeatures are defined to avoid layout shape-to-shape spatialrelationships which would introduce adverse lithographic interactionwithin the layout that cannot be accurately predicted and mitigated withhigh probability. However, it should be understood that changes indirection of gate level features within their gate level layout channelsare acceptable when corresponding lithographic interactions arepredictable and manageable.

It should be understood that each of the gate level features, regardlessof function, is defined such that no gate level feature along a givengate electrode track is configured to connect directly within the gatelevel to another gate level feature defined along a different gateelectrode track without utilizing a non-gate level feature. Moreover,each connection between gate level features that are placed withindifferent gate level layout channels associated with different gateelectrode tracks is made through one or more non-gate level features,which may be defined in higher interconnect levels, i.e., through one ormore interconnect levels above the gate level, or by way of localinterconnect features at or below the gate level.

Exemplary Embodiments

In one embodiment, a cell circuit of a semiconductor device isdisclosed. The cell circuit includes a substrate and a number oflinear-shaped diffusion fins defined to extend over the substrate in afirst direction, so as to extend parallel to each other. Each of thenumber of linear-shaped diffusion fins is defined to project upward fromthe substrate along their extent in the first direction. In oneembodiment, each of the number of linear-shaped diffusion fins is formedfrom a doped silicon-based material to form either a p-type or an n-typetransistor diffusion region.

The cell circuit also includes a number of gate level structures definedto extend in a conformal manner over some of the number of linear-shapeddiffusion fins. Portions of each gate level structure that extend overany of the number of linear-shaped diffusion fins extend in a seconddirection that is substantially perpendicular to the first direction.Portions of each gate level structure that extend over any of the numberof linear-shaped diffusion fins form gate electrodes of a correspondingtransistor. In one embodiment, each of the number of gate levelstructures is formed from an electrically conductive material.

In one embodiment, the number of linear-shaped diffusion fins arepositioned on diffusion tracks that correspond to virtual lines of adiffusion fin virtual grate. The diffusion tracks extend in the firstdirection over the substrate. In a particular embodiment, the diffusiontracks are positioned based on a fixed diffusion track pitch. The fixeddiffusion track pitch corresponds to an equal perpendicular spacingbetween adjacent diffusion tracks. In one instance of this particularembodiment, a size of the fixed diffusion track pitch is set at a singleexposure lithographic limit.

Also, in one embodiment, the first direction corresponds to a widthdirection of the cell circuit. In this embodiment, the fixed diffusiontrack pitch is related to a height of the cell circuit, such that acontinuity of the fixed diffusion track pitch is maintained acrossboundaries of the cell circuit to form a global set of equally spaceddiffusion tracks across a group of neighboring cell circuits. In oneinstance of this embodiment, the height of the cell circuit is aninteger multiple of the fixed diffusion track pitch.

The number of linear-shaped diffusion fins are positioned on diffusiontracks as needed for cell circuit functionality. In various embodiments,some diffusion tracks are partially filled with linear-shaped diffusionfins, some diffusion tracks are completely filled with linear-shapeddiffusion fins, some diffusion tracks are vacant and do not have alinear-shaped diffusion fin positioned thereon, or any combinationthereof.

In one embodiment, the portions of the gate level structures that extendover any of the number of linear-shaped diffusion fins are positioned ongate electrode tracks that correspond to virtual lines of a gate levelvirtual grate. The gate electrode tracks extend in the second directionover the substrate. In one embodiment, the gate electrode tracks arepositioned based on a fixed gate electrode track pitch. The fixed gateelectrode track pitch corresponds to an equal perpendicular spacingbetween adjacent gate electrode tracks.

In one embodiment, the second direction corresponds to a heightdirection of the cell circuit. The fixed gate electrode track pitch canbe related to a width of the cell circuit, such that a continuity of thefixed gate electrode track pitch is maintained across boundaries of thecell circuit to form a global set of equally spaced gate electrodetracks across a group of neighboring cell circuits. In one embodiment,the width of the cell circuit is an integer multiple of the fixed gateelectrode track pitch.

The gate level structures are positioned on gate electrode tracks asneeded for cell circuit functionality. In various embodiments, some gateelectrode tracks are partially filled with gate level structures, somegate electrode tracks are completely filled with gate level structures,some gate electrode tracks are vacant and do not have a gate levelstructure positioned thereon, or any combination thereof.

Also, in another embodiment, the gate level structures are positioned tomaximally fill gate electrode tracks. In this embodiment, breaks aredefined between multiple gate level structures along individual gateelectrode tracks as needed for cell circuit functionality. In oneinstance of this embodiment, the breaks defined between multiple gatelevel structures along individual gate electrode tracks are uniform insize through the cell circuit.

The cell circuit can also include a number of local interconnectstructures defined between neighboring gate level structures so as toextend in the second direction parallel to the neighboring gate levelstructures. The number of local interconnect structures are formed of anelectrically conductive material. Also, the number of local interconnectstructures are formed at or below a gate level of the cell circuit.Additionally, the cell circuit can include a number of higher levelinterconnect structures defined in an interconnect level above a gatelevel of the cell circuit. In one embodiment, the number of higher levelinterconnect structures are linear-shaped and extend in the firstdirection. In another embodiment, the number of higher levelinterconnect structures are unrestricted with regard to shape and areformed as necessary for circuit functionality. The cell circuit can alsoinclude a number of contact structures, and any other type of structurepreviously discussed with regard to the examples of FIGS. 2A-2C.

In another embodiment, a semiconductor device cell layout is disclosed.This embodiment is essentially a layout of the cell circuit embodimentdiscussed above. Therefore, any features discussed above with regard tothe cell circuit embodiment can be represented within this cell layoutembodiment. The cell layout includes a diffusion level layout and a gatelevel layout. The diffusion level layout includes a number of diffusionfin layout shapes defined to extend in only a first direction across thecell layout, so as to extend parallel to each other. The number ofdiffusion fin layout shapes correspond to diffusion fin structuresdefined to project upward from a substrate along their extent in thefirst direction.

In one embodiment, the diffusion fin layout shapes are positioned ondiffusion tracks that correspond to virtual lines of a diffusion finvirtual grate. The diffusion tracks extend in the first direction acrossthe cell layout. In one embodiment, the diffusion tracks are positionedbased on a fixed diffusion track pitch. The fixed diffusion track pitchcorresponds to an equal perpendicular spacing between adjacent diffusiontracks. In one embodiment, the first direction corresponds to a widthdirection of the cell layout. In this embodiment, the fixed diffusiontrack pitch is related to a height of the cell layout, such that acontinuity of the fixed diffusion track pitch is maintained acrossboundaries of the cell layout to form a global set of equally spaceddiffusion tracks across a group of neighboring cell layouts. In oneinstance of this embodiment, the height of the cell layout is an integermultiple of the fixed diffusion track pitch.

The gate level layout of the cell layout includes a number of gate levellayout shapes defined to extend in a second direction across the celllayout that is substantially perpendicular to the first direction. Thegate level layout shapes correspond to gate level structures defined toextend in a conformal manner over some of the diffusion fin structureswhich correspond to the diffusion fin layout shapes. Portions of eachgate level structure that extend over any of the diffusion finstructures form gate electrodes of a corresponding transistor.

In one embodiment, portions of the gate level layout shapes that extendover any of the diffusion fin layout shapes are positioned on gateelectrode tracks that correspond to virtual lines of a gate levelvirtual grate. The gate electrode tracks extend in the second directionacross the cell layout, i.e., perpendicular to the first direction. Inone embodiment, the gate electrode tracks are positioned based on afixed gate electrode track pitch. The fixed gate electrode track pitchcorresponds to an equal perpendicular spacing between adjacent gateelectrode tracks. In one embodiment, the second direction corresponds toa height direction of the cell layout. In this embodiment, the fixedgate electrode track pitch is related to a width of the cell layout,such that a continuity of the fixed gate electrode track pitch ismaintained across boundaries of the cell layout to form a global set ofequally spaced gate electrode tracks across a group of neighboring celllayouts. In one instance of this embodiment, the width of the celllayout is an integer multiple of the fixed gate electrode track pitch.It should be understood that the cell layout can also include a numberof additional layout shapes and levels corresponding to other circuitstructures, including any other type of circuit structure previouslydiscussed with regard to the examples of FIGS. 2A-2C.

It should be understood that any cell layout incorporating finfettransistors as disclosed herein can be stored in a tangible form, suchas in a digital format on a computer readable medium. For example, agiven cell layout can be stored in a layout data file, and can beselectable from one or more libraries of cells. The layout data file canbe formatted as a GDS II (Graphic Data System) database file, an OASIS(Open Artwork System Interchange Standard) database file, or any othertype of data file format suitable for storing and communicatingsemiconductor device layouts. Also, multi-level layouts of a cellincorporating finfet transistors as disclosed herein can be includedwithin a multi-level layout of a larger semiconductor device. Themulti-level layout of the larger semiconductor device can also be storedin the form of a layout data file, such as those identified above.

Also, the invention described herein can be embodied as computerreadable code on a computer readable medium. For example, the computerreadable code can include a layout data file within which a layout of acell incorporating finfet transistors as disclosed herein is stored. Thecomputer readable code can also include program instructions forselecting one or more layout libraries and/or cells that include finfettransistors as disclosed herein. The layout libraries and/or cells canalso be stored in a digital format on a computer readable medium.

The computer readable medium mentioned herein is any data storage devicethat can store data which can thereafter be read by a computer system.Examples of the computer readable medium include hard drives, networkattached storage (NAS), read-only memory, random-access memory, CD-ROMs,CD-Rs, CD-RWs, magnetic tapes, and other optical and non-optical datastorage devices. Multiple computer readable media distributed within anetwork of coupled computer systems can also be used to store respectiveportions of the computer readable code such that the computer readablecode is stored and executed in a distributed fashion within the network.

It should be further understood that any cell layout incorporatingfinfet transistors as disclosed herein can be manufactured as part of asemiconductor device or chip. In the fabrication of semiconductordevices such as integrated circuits, memory cells, and the like, aseries of manufacturing operations are performed to define features on asemiconductor wafer. The wafer includes integrated circuit devices inthe form of multi-level structures defined on a silicon substrate. At asubstrate level, transistor devices with diffusion regions and/ordiffusion fins are formed. In subsequent levels, interconnectmetallization lines are patterned and electrically connected to thetransistor devices to define a desired integrated circuit device. Also,patterned conductive layers are insulated from other conductive layersby dielectric materials.

While this invention has been described in terms of several embodiments,it will be appreciated that those skilled in the art upon reading thepreceding specifications and studying the drawings will realize variousalterations, additions, permutations and equivalents thereof. Therefore,it is intended that the present invention includes all such alterations,additions, permutations, and equivalents as fall within the true spiritand scope of the invention.

What is claimed is:
 1. An integrated circuit, comprising: a substrate; adiffusion fin of a first diffusion type extending over the substrate; afirst local interconnect structure electrically contacting the diffusionfin of the first diffusion type; a diffusion fin of a second diffusiontype extending over the substrate; a second local interconnect structureelectrically contacting the diffusion fin of the second diffusion type,the first and second local interconnect structures extending lengthwisealong a same line; a first gate structure extending over andelectrically contacting both the diffusion fin of the first diffusiontype and the diffusion fin of the second diffusion type, the first gatestructure extending along at least a portion of a first side of thefirst local interconnect structure and along at least a portion of afirst side of the second local interconnect structure; and a second gatestructure extending over and electrically contacting both the diffusionfin of the first diffusion type and the diffusion fin of the seconddiffusion type, the second gate structure extending along at least aportion of a second side of the first local interconnect structure andalong at least a portion of a second side of the second localinterconnect structure.
 2. The integrated circuit as recited in claim 1,wherein the first local interconnect structure is linear-shaped, andwherein the second local interconnect structure is linear-shaped.
 3. Theintegrated circuit as recited in claim 2, wherein the first gatestructure is linear-shaped, and wherein the second gate structure islinear-shaped.
 4. The integrated circuit as recited in claim 3, whereinthe first gate structure is spaced apart from the first localinterconnect structure by a first distance as measured perpendicularlybetween lengthwise centerlines of the first gate structure and the firstlocal interconnect structure, and wherein the second gate structure isspaced apart from the first local interconnect structure by a seconddistance as measured perpendicularly between lengthwise centerlines ofthe second gate structure and the first local interconnect structure,wherein the second distance is substantially equal to the firstdistance.
 5. The integrated circuit as recited in claim 1, wherein anoverall length of the first gate structure as measured along alengthwise centerline of the first gate structure is substantially equalto an overall length of the second gate structure as measured along alengthwise centerline of the second gate structure.
 6. The integratedcircuit as recited in claim 5, wherein a first end of the first gatestructure and a first end of the second gate structure are positioned ata first line that extends perpendicular to the lengthwise centerline ofthe first local interconnect structure, and wherein a second end of thefirst gate structure and a second end of the second gate structure arepositioned at a second line that extends perpendicular to the lengthwisecenterline of the second local interconnect structure.
 7. The integratedcircuit as recited in claim 1, wherein a width of the first gatestructure as measured perpendicular to a lengthwise centerline of thefirst gate structure is substantially equal to a width of the secondgate structure as measured perpendicular to a lengthwise centerline ofthe second gate structure.
 8. The integrated circuit as recited in claim1, wherein a width of the first local interconnect structure as measuredperpendicular to a lengthwise centerline of the first local interconnectstructure is substantially equal to a width of the second localinterconnect structure as measured perpendicular to a lengthwisecenterline of the second local interconnect structure.
 9. The integratedcircuit as recited in claim 1, wherein the first local interconnectstructure is electrically connected to a first power line, and whereinthe second local interconnect structure is electrically connected to asecond power line.
 10. The integrated circuit as recited in claim 1,further comprising: a plurality of diffusion fins of the first diffusiontype, wherein said diffusion fin of the first diffusion type is one ofthe plurality of diffusion fins of the first diffusion type, wherein thefirst local interconnect structure electrically contacts each of theplurality of diffusion fins of the first diffusion type.
 11. Theintegrated circuit as recited in claim 10, wherein the first gatestructure extends over and electrically contacts each of the pluralityof diffusion fins of the first diffusion type.
 12. The integratedcircuit as recited in claim 11, wherein the second gate structureextends over and electrically contacts each of the plurality ofdiffusion fins of the first diffusion type.
 13. The integrated circuitas recited in claim 12, further comprising: a plurality of diffusionfins of the second diffusion type, wherein said diffusion fin of thesecond diffusion type is one of the plurality of diffusion fins of thesecond diffusion type, wherein the second local interconnect structureelectrically contacts each of the plurality of diffusion fins of thesecond diffusion type.
 14. The integrated circuit as recited in claim13, wherein the plurality of diffusion fins of the first diffusion typeincludes three diffusion fins of the first diffusion type.
 15. Theintegrated circuit as recited in claim 14, wherein the plurality ofdiffusion fins of the second diffusion type includes three diffusionfins of the second diffusion type.
 16. The integrated circuit as recitedin claim 1, wherein the first gate structure and the second gatestructure are positioned in accordance with a fixedcenterline-to-centerline pitch.
 17. The integrated circuit as recited inclaim 1, further comprising: a third local interconnect structureelectrically contacting both the diffusion fin of the first diffusiontype and the diffusion fin of the second diffusion type.
 18. Theintegrated circuit as recited in claim 17, wherein the third localinterconnect structure is linear-shaped.
 19. The integrated circuit asrecited in claim 18, wherein the third local interconnect structure iselectrically connected to a higher level interconnect structure.
 20. Theintegrated circuit as recited in claim 18, wherein the third localinterconnect structure is positioned next to either the first gatestructure or the second gate structure.